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A4447 High Voltage Step Down Regulator
Features and Benefits
Wide input voltage range: 8 to 50 V Integrated low RDS(on) DMOS switch 2 A continuous output current Adjustable fixed off-time Highly efficient Adjustable output: 0.8 to 24 V Small package with exposed thermal pad
Description
The A4447 is a 2 A, high efficiency general-purpose buck regulator designed for a wide variety of applications. The output voltage is adjustable from 0.8 to 24 V, based on a resistor divider and the 0.8 V 2 % reference. External components include an external clamping diode, inductor, and filter capacitor. The off-time is determined by an external resistor to ground. It operates in both continuous and discontinuous modes to maintain light load regulation. An internal blanking circuit is used to filter out transients due to the reverse recovery of the external clamp diode. Typical blanking time is 200 ns. This new device is ideal for various end products including applications with 8 to 50 V input voltage range and require up to 2 A output current, such as uninterruptible power supplies, point of sale (POS) applications, and industrial applications with 24 or 36 V bus. Applications include: Printer power supplies Office automation equipment POS thermal, laser, photo, and inkjet printers Tape drives Industrial applications
Package: 8 pin SOIC with exposed thermal pad (suffix LJ)
Approximate Scale 1:1
Typical Application
+42 V CBOOT 0.01 F CIN2 BOOT VIN CIN1 0.22 F
Efficiency vs. Output Current
90 85 5 3.3 80 75 70 65 60 0 500 1000 1500 2000 1.8 1.5 VOUT (V)
ENB A4447 TSET RTSET 54 k GND
LX
L1
VBIAS R1 2.87 k FB R2 910 CBYP 0.22 F
VOUT 3.3 V 2A
ESR COUT 220 F 25 V
Efficiency %
D1
IOUT (mA)
Data is for reference only. Efficiency data from circuit shown in left panel.
A4447-DS, Rev. 1
A4447
High Voltage Step Down Regulator
Absolute Maximum Ratings
Characteristic VIN Supply Voltage VBIAS Input Voltage SW Switching Voltage ENB Input Voltage Range Operating Ambient Temperature Range Junction Temperature Storage Temperature Symbol VIN VBIAS VS VENB TA TJ(max) Tstg Conditions Min. - -0.3 -1 -0.3 -20 - -55 Typ. - - - - - - - Max. 50 7 - 7 85 150 150 Units V V V V C C C
*Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current ratings, or a junction temperature, TJ, of 150C.
Package Thermal Characteristics*
Package LJ RJA (C/W) 35 PCB 4-layer
* Additional information is available on the Allegro website.
Ordering Information Use the following complete part numbers when ordering:
Part Number A4447SLJTR-T Packing 13-in. reel, 3000 pieces/reel Description LJ package, SOIC surface mount with exposed thermal pad; leadframe plating 100% matte tin.
Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
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A4447
High Voltage Step Down Regulator
Functional Block Diagram
BOOT Boot Charge
VIN
+
VIN
LX L1 D1 ESR COUT
VOUT
ENB C
Switch Disable
Switch PWM Control
TSET I_Peak
+
-
I_Demand Error
COMP GND
+
VBB UVLO TSD
Soft Start Ramp Generation
-
Clamp
CBYP
-
FB
Bias Supply
VBIAS
VBIAS is connected to VOUT when VOUT target is between 3.3 and 5 V
0.8 V
Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
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A4447
High Voltage Step Down Regulator
ELECTRICAL CHARACTERISTICS1,2 at TA = 25C, VIN = 8 to 50 V (unless noted otherwise)
Characteristics Symbol Test Conditions VENB = LOW, IOUT = 0 mA, VIN = 42 V, VBIAS = VOUT VIN Quiescent Current3 IVIN(Q) VENB = LOW, IOUT = 0 mA, VIN = 42 V, VBIAS < 3 V VENB = HIGH VBIAS Input Current Buck Switch On Resistance Fixed Off-Time Proportion Feedback Voltage Output Voltage Regulation Feedback Input Bias Current Soft Start Time Buck Switch Current Limit ENB Open Circuit Voltage ENB Input Voltage Threshold ENB Input Current VIN Undervoltage Threshold VIN Undervoltage Hysteresis Thermal Shutdown Temperature Thermal Shutdown Hysteresis
1Negative 2Specifications
Min. - - - - - - -15 0.784 -3 -400 5
Typ. 0.90 4.4 - 3.5 450 650 - 0.8 - -100 10 - - - - - 6.9 - 165 15
Max. 1.35 6.35 100 5 - - 15 0.816 3 100 15 3 1.2 7 1.0 -1 7.2 1.1 - -
Units mA mA A mA m m % V % nA ms A A V V A V V C C
IBIAS RDS(on) toff VFB VOUT IFB tss ICL VOC VENB(0) IENB(0) VUVLO VUVLO(hys) TJTSD TJTSD(hys)
VBIAS = VOUT TA = 25C, IOUT = 2 A TA = 125C, IOUT = 2 A Based on calculated value IOUT = 0 mA to 2 A
VFB > 0.4 V VFB < 0.4 V Output disabled LOW level input (Logic 0), output enabled VENB = 0 V VIN rising VIN falling Temperature increasing Recovery = TJTSD - TJTSD(hys)
2.2 0.5 2.0 - -10 6.6 0.7 - -
current is defined as coming out of (sourcing) the specified device pin. over the junction temperature range of 0C to 125C are assured by design and characterization. 3VBIAS is connected to VOUT when the V OUT target is between 3.3 and 5 V.
Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
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A4447
High Voltage Step Down Regulator
Functional Description
The A4447 is a fixed off-time, current mode controlled, buck regulator. The regulator requires an external clamping diode, inductor, and filter capacitor. It operates in both continuous and discontinuous modes. An internal blanking circuit is used to filter out transients resulting from the reverse recovery of the external clamp diode. Typical blanking time is 200 ns. The value of a resistor between the TSET and GND determines the fixed off-time (see graph in the tOFF section). VOUT. The output voltage is adjustable from 0.8 to 24 V, set by an external resistor divider. The voltage can be calculated with the following formula: VOUT = VFB x (1 + R1/R2) (1) Light Load Regulation. To maintain voltage regulation during light load conditions, the switching regulator enters a cycle-skipping mode. As the output current decreases, there remains some energy that is stored during the power switch minimum on-time. In order to prevent the output voltage from rising, the regulator skips cycles once it reaches the minimum on-time, effectively making the off-time larger. Soft Start. An internal ramp generator and counter allow the output to slowly ramp up. This limits the maximum demand on the external power supply by controlling the inrush current required to charge the external capacitor and any DC load at startup. Internally, the ramp is set to 10 ms nominal rise time. During soft start, current limit is 2.2 A minimum. The following conditions are required to trigger a soft start: * VIN > 6 V * ENB pin input falling edge * Reset of a TSD (thermal shut down) event VBIAS. To improve overall system efficiency, the regulator output, VOUT, is connected to the VBIAS input to supply the operating bias current during normal operating conditions. During startup the circuitry is run off of the VIN supply. VBIAS should be connected to VOUT when the VOUT target level is between 3.3 and 5 V. If the output voltage is less than 3.3 V, then the A4447 can operate with an internal supply and pay a penalty in efficiency, as the bias current will come from the high voltage supply, VIN. VBIAS can also be supplied with an external voltage source. No power-up sequencing is required for normal operation. ON/OFF Control. The ENB pin is externally pulled to ground to enable the device and begin the soft start sequence. When the ENB is open circuited, the switcher is disabled and the output decays to 0 V. Protection. The buck switch will be disabled under one or more
of the following fault conditions: * VIN < 6 V * ENB pin = open circuit * TSD fault When the device comes out of a TSD fault, it will go into a soft start to limit inrush current. tOFF. The value of a resistor between the TSET pin and ground determines the fixed off-time. The formula to calculate tOFF (s) is: 1- 0.03 x VBIAS (2) , tOFF = RTSET 10.2 x 109 where RTSET (k) is the value of the resistor. Results are shown in the following graph:
Off-Time Setting versus Resistor Value
200 180 160 140
RTSET (k)
120 100 80 60 40 20 0 1 2 3 4 5
VBIAS = 5 V VBIAS = 3.3 V
6
7
8
9
10
11 12 13 14 15
16
tOFF (s)
The RTSET resistor should be not smaller than 7.65 k 2% to prevent very short off-times from violating the minimum on-time of the switcher. Shorted Load. If the voltage on the FB pin falls below 0.4 V, the regulator will invoke a 0.85 A typical overcurrent limit to handle the shorted load condition at the regulator output. For low output voltages at power up and in the case of a shorted output, the offtime is extended to prevent loss of control of the current limit due to the minimum on-time of the switcher. The extension of the off-time is based on the value of the TSET multiplier and the FB voltage, as shown in the following table:
VFB (V) < 0.16 < 0.32 < 0.5 > 0.5 TSET Multiplier 8 x tOFF 4 x tOFF 2 x tOFF tOFF
Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
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A4447
High Voltage Step Down Regulator
Component Selection
L1. The inductor must be rated to handle the total load current. The value should be chosen to keep the ripple current to a reasonable value. The ripple current, IRIPPLE, can be calculated by: IRIPPLE = VL(OFF) x tOFF / L VL(OFF) = VOUT + Vf + IL(AV) x RL Example: Given VOUT = 5 V, Vf = 0.55 V, VIN = 42 V, ILOAD = 0.5 A, power inductor with L = 180 H and RL = 0.5 Rdc at 55C, tOFF = 7 s, and RDS(on) = 1 . Substituting into equation 4: VL(OFF) = 5 V + 0.55 V+ 0.5 A x 0.5 = 5.8 V Substituting into equation 3: IRIPPLE = 5.8 V x 7 s / 180 H = 225 mA The switching frequency, fSW, can then be estimated by: fSW = 1 / ( tON + tOFF ) tON = IRIPPLE x L / VL(ON) VL(ON) = VIN - IL(AV) x RDS(on) - IL(AV) x RL- VOUT Substituting into equation 7: VL(ON) = 42 V - 0.5 A x 1 - 0.5 A x 0.5 - 5 V = 36 V Substituting into equation 6: tON = 225 mA x 180 H / 36 V = 1.12 s (5) (6) (7) (3) (4) Substituting into equation 7: fSW = 1 / (7 s +1.12 s) = 123 kHz Higher inductor values can be chosen to lower the ripple current. This may be an option if it is required to increase the total maximum current available above that drawn from the switching regulator. The maximum total current available, ILOAD(MAX) , is: ILOAD(MAX) = ICL(min) - IRIPPLE / 2 (8)
where ICL(min) is 2.2 A, from the Electrical Characteristics table. D1. The Schottky catch diode should be rated to handle 1.2 times the maximum load current. The voltage rating should be higher than the maximum input voltage expected during all operating conditions. The duty cycle for high input voltages can be very close to 100%. COUT. The main consideration in selecting an output capacitor is voltage ripple on the output. For electrolytic output capacitors, a low-ESR type is recommended. The peak-to-peak output voltage ripple is simply IRIPPLE x ESR. Note that increasing the inductor value can decrease the ripple current. The minimum voltage rating of the capacitor is 10 V. However, because ESR decreases with voltage, the most cost-effective choice may be rated higher in voltage. It is recommended that the ESR be less than 100 m.
Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
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A4447
High Voltage Step Down Regulator
conditions the resistance on the TSET pin remains as close to the curve as possible. The RTEST Selection table shows recommended RTSET values based on common operating conditions. For other operating conditions, refer to the RTSET Value Selection graph. FB Resistor Selection. The impedance of the FB network should be kept low to improve noise immunity. Large value resistors can pick up noise generated by the inductor, which can affect voltage regulation of the switcher.
Recommended Common Values VIN (V) 42 42 42 42 24 24 24 24 12 12 12 12 VOUT (V) 5 3.3 1.8 1.5 5 3.3 1.8 1.5 5 3.3 1.8 1.5 VIN / VOUT 8.4 12.7 23.3 28 4.8 7.3 13.3 16 2.4 3.6 6.6 8 RTSET Value (k) 37.4 54.9 90.9 105 20.0 32.4 54.9 66.5 7.68 13.7 30.1 37.4
RTSET Selection. Correct selection of RTSET values will ensure that minimum on time of the switcher is not violated and prevent the switcher from cycle skipping. For a given VIN to VOUT ratio, RTSET must be greater than or equal to the value defined by the curve in the RTEST Value Selection graph below. Note. The curve represents the minimum RTSET value. When calculating RTSET , be sure to use VIN(max) / VOUT(min). Resistor tolerance should also be considered, so that under all operating
RTSET Value Selection* Selection Graph
70 65 60 55 50
VIN / VOUT
45 40 35 30 25 20 15 10 5 0 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210
RTSET (k)
*The RTSET resistor should be not smaller than 7.65 k 2% to prevent very short off-times from violating the minimum on-time of the switcher.
Recommended Components Component L1 D1 CBYP CBOOT CIN Sumida 68 H NIEC Schottky Barrier Diode 60 V TO-252AA Ceramic X7A 0.22 F 100 V Ceramic X7A 0.01 F 100 V Electrolytic 100 F 50 V; must be able to handle worst case ripple curent Ceramic X7A 0.22 F 50 V United Chemi-Con PXA 220 F 16 V Low ESR COUT Rubycon ZL 220 F 25 V Low ESR (Option 1) VOUT 1.5 V R1 R2 1.30 k 1.47 k 1.8 V 2.55 k 2.00 k 3.3 V 2.87 k 0.910 k 5V 6.34 k 1.20 k
Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
Description
Part Number RCH1216BNP-680K NSQ03A06 Generic Generic Generic Generic PXA16VC221MJ12TP 25ZL220M8x11.5 EEUFM1E221
Panasonic FM 220 F 25 V Low ESR (Option 2)
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A4447
High Voltage Step Down Regulator
Recommended PCB Layout
In order to minimize the effects of ground bounce and offset issues, it is important to have a low impedance ground located very close to the device. This grounding scheme is known as star grounding. It is likely that a ground plane will be necessary to meet thermal requirements. The recommended land pattern illustrates how to create a low impedance ground that will also assist with removing thermal energy from the device. The input capacitor must be placed as close as possible to the VIN terminal because during the on cycle it is responsible for supplying the current to the switcher. During the off cycle, the current path is from the negative terminal of the COUT cap, through the diode and inductor, and then to the load. As a result, COUT and the rectifier diode must share the connection at the negative terminal of the CIN capacitor in order to reduce ground bounce when the diode is conducting.
The inductor should be connected as close as possible to the switching node to minimize noise. Some applications may require a shielded inductor due to EMI restrictions. This will depend on the application and parameters defined by the system that will host the regulator. The high voltage-switching node could affect RTSET. If longer off-times are used, the resistance on the RTSET pin can be quite large. When designing the layout, try to keep RTSET away from the inductor and switching node. It is also beneficial to keep the trace as short as possible to reduce the effect of noise injection. Because of this layout guideline, the TSET pin is located on the other side of the device, away from the switching node. The FB resistor network should have a lower impedance to avoid interference from the switching node. Because the impedance on the FB node can be controlled, it is not as critical to keep the network isolated. It is important to keep the ground trace short so that ground bounce cannot effect the output voltage regulation.
Star Ground
CIN1 VIN GND CIN2 CBOOT U1 D1 GND RTSET R2 R1 GND CBYP L1 VOUT COUT GND
VIN
CBOOT 1
BOOT ENB VIN LX VBIAS FB
CIN2
CIN1
A4447
PAD
D1
RTSET
TSET GND
CBYP R2 R1 L1 COUT
VOUT
Exposed copper thermal ground area on the unpopulated side of the PCB The large star ground area on the populated side of the PCB, shown in the diagram as the GND nodes, supports high current throughput, and allows the VOUT node to be located as close as practical to the A4447 (U1). Thermal conduction from the A4447 is enhanced by direct contact of its exposed thermal pad to the smaller ground area under the A4447. This area is connected by thermal vias to the large copper ground plane on the unpopulated side of the PCB.
Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
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A4447
High Voltage Step Down Regulator
Package LJ, 8 Pin SOIC
4.90 0.10 8
8 0 0.25 0.17
0.65
8
1.27
1.75
2.41 NOM
B A
3.90 0.10
6.00 0.20
1.04 REF
2.41
5.60
1
2 3.30 NOM 1.27 0.40 0.25 BSC Branded Face SEATING PLANE GAUGE PLANE C
1
2 3.30
PCB Layout Reference View
8X 0.10 C 0.51 0.31 1.27 BSC
SEATING PLANE 1.70 MAX 0.15 0.00
C
For Reference Only; not for tooling use (reference MS-012BA) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B C Exposed thermal pad (bottom surface); dimensions may vary with device Reference land pattern layout (reference IPC7351 SOIC127P600X175-9AM); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
Terminal List Table Pin Out Diagram
BOOT ENB TSET GND 1 2 3 4 Pad 8 7 6 5 VIN LX VBIAS FB
Number 1 2 3 4 5 6 7 8
Name BOOT ENB TSET GND FB VBIAS LX VIN
Description Gate drive boost node On/off control; logic input Off-time setting Ground Feedback for adjustable regulator Bias supply input Buck switching node Supply input
Copyright (c)2008-2009, Allegro MicroSystems, Inc. The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro's products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com
Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
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